Riviera-PRO

Riviera-PRO: Functional Verification Platform

Riviera-PRO is a functional verification platform used for testing and debugging complex hardware designs. It enables comprehensive testing and analysis for verifying hardware compliance and robustness.

What is Riviera-PRO?

Riviera-PRO is a comprehensive functional verification platform used by hardware design and verification teams for testing complex System-on-Chip (SoC) designs. It provides a robust environment for pre-silicon validation, debugging, and analysis of register transfer level (RTL) designs written in Verilog, SystemVerilog, VHDL, and SystemC.

Key capabilities and benefits of Riviera-PRO include:

• Advanced debugging with features like data-path viewer, visual error tracking, configurable warnings, and procedural assertions
• Powerful verification planning, reuse, and coverage analysis for efficient testing
• Fast simulation and compilation for Verilog, SystemVerilog, VHDL, and SystemC
• Integration with other tools like formal verification, virtual prototyping, and visualization
• Support for the Universal Verification Methodology (UVM) and other methodologies
• Runs on both Linux and Windows platforms

Riviera-PRO helps teams validate intricate designs, achieve confidence in the correctness of the implementation, and meet project schedules. Its advanced debugging and analysis capabilities combined with fast simulation performance make it a popular choice among leading semiconductor and systems companies.

Riviera-PRO Features

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